High-frequency bipolar transistor and method for the production thereof

ABSTRACT

A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a collector contact adjoining a collector connection region. A first insulation layer is disposed on the base connection region. The collector connection region contains a buried layer, which connects the collector contact to a collector zone. A silicide or salicide region is provided on the buried layer and connects the collector contact to the collector zone in a low-impedance manner. A second insulation layer is disposed on the collector connection region but not on the silicide region.

RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.11/254,502, filed on Oct. 20, 2005, now U.S. Pat. No. 7,719,088 whichwas a continuation of International Application PCT/EP2004/050335, filedon Mar. 19, 2004, which claims the benefit of priority to German PatentApplication DE 10 2003 10318422.8 filed on Apr. 23, 2003, all of whichare herein incorporated by reference in their entirety.

BACKGROUND

The invention relates to a high-frequency bipolar transistor comprisingat least an emitter contact adjoining an emitter connection region, abase contact adjoining a base connection region, a collector contactadjoining a collector connection region, a buried layer being providedas the collector connection region, said buried layer connecting thecollector contact to the collector zone. Such a high-frequency bipolartransistor is known from U.S. Pat. No. 5,773,350.

The invention furthermore relates to a method for the production of ahigh-frequency bipolar transistor, in which a collector connectionregion, a collector zone, at least on the collector connection region afirst insulation layer, a base zone, a base connection region, at leaston the base connection region a second insulation layer and an emitterconnection region are made available, the collector connection regionbeing embodied as a buried layer. Such a method is known from DE19958062.

The equation below holds true for a bipolar transistor:

$\frac{1}{2\;\pi\; f_{T}} = {\tau_{f} + {\left( {R_{C} + R_{E}} \right)C_{BC}} + {\frac{C_{BE} + C_{BC}}{I_{C}}U_{T}}}$where f_(T) is the transition frequency, ô_(f) is the transit time,R_(C) is the collector resistance, R_(E) is the emitter resistance,C_(BC) is the base-collector capacitance, C_(BE) is the base-emittercapacitance, I_(C) is the collector current and U_(T) is the thermalvoltage.

As the collector current I_(C) increases, the term proportional to1/I_(C) becomes smaller and smaller. The principal proportion of thetransition frequency f_(T) is therefore given, besides the transit timeô_(f), in particular by the collector resistance R_(C) and the emitterresistance R_(E). In present-day transistors, however, the transitionfrequency f_(T) is given, besides the transit time ô_(f), principally bythe collector resistance R_(C), which is typically an order of magnitudegreater than the emitter resistance R_(E). Therefore, the collectorresistance must be minimized for fast transistors.

In order to obtain a low-impedance collector connection, use isgenerally made of a highly doped buried layer. This layer is produced atthe beginning of the transistor production. After it, a semiconductorlayer in which the emitter, base and collector zones are produced isgrown epitaxially on said low-impedance layer. The highly doped buriedlayer is connected by means of a metallic collector contact and led tothe surface of the bipolar transistor. This is described for example inU.S. Pat. No. 5,773,350 and DE 19958062.

In general, a collector contact is provided on only one side of thetransistor. If the buried layer is connected not just on one side butalso on the opposite side or even annularly around the entire transistorzone, lower collector resistances may be obtained. Such transistorconfigurations have a resistance with a magnitude approximately a halfor a quarter that of a configuration having only a single collectorcontact, since the collector current can flow not just toward one side,but toward two or four sides.

However, this embodiment entails significant disadvantages. Firstly, thetransistor dimensions are enlarged by the additional collector contactzones. This leads to higher production costs on account of the largersubstrate area required. Secondly, the collector-substrate capacitanceof the bipolar transistor is also increased proportionally to theincreasing area of the buried layer. This in turn leads to adverseeffects, such as a higher gate delay time or increased power consumptionof integrated circuits.

BRIEF SUMMARY

Accordingly, it is an object of the present invention to present ahigh-frequency bipolar transistor which combines a small spacerequirement with a low collector resistance and thus a high transitionfrequency. Furthermore, it is an object to achieve a method for theproduction of such a bipolar transistor without additional processcomplexity.

According to the invention, the object is achieved by means of ahigh-frequency bipolar transistor of the type mentioned in theintroduction which has a silicide region on the buried layer, saidsilicide region connecting the collector contact to the collector zonein a low-impedance manner. What is thereby achieved is that thecollector resistance is reduced, because the collector zone of thebipolar transistor is virtually connected from all sides even though acollector contact is provided only on one side.

The invention is based on the insight that sheet resistances ofapproximately 1 ohm/sq can be obtained by means of a silicide region onthe buried layer. By contrast, a corresponding buried layer having athickness of a few μm, after doping, only has sheet resistances ofapproximately 10 ohm/sq. The sheet resistance of the buried layer andthus the collector connection resistance can therefore be reduced up toapproximately one order of magnitude by means of a silicide region. Thesheet resistance is then so low that even when contact is made with theburied layer on only a single side of the transistor, the collectorconnection region is connected in a low-impedance manner virtually fromall sides by means of the silicide region.

In a typical configuration of the bipolar transistor according to theinvention, the silicide region has a thickness in the range of between10 and 200 nm; the thickness of the silicide region is preferablyapproximately 100 nm.

The silicide region typically contains at least one transition metal.The transition metal used may be titanium, cobalt, nickel, platinum ortantalum, for example, which form a corresponding transition silicidewith silicon. The same metal as is required anyway in the overallprocess for siliciding other zones such as e.g. the base connectionregion or source, drain and gate zones of CMOS transistors is preferablyused for the siliciding. Consequently, the transition metal for formingthe silicide region can be integrated into the transistor withoutadditional costs.

In a particularly advantageous configuration of the high-frequencybipolar transistor according to the invention, the silicide regioncontains titanium or cobalt. These transition metals ensure aparticularly low sheet resistance of the buried layer. A metal thatyields a minimum sheet resistance is thus chosen.

The siliciding or formation of the silicide region typically bringsabout a reduction of the sheet resistance from approximately 100 ohm/sqof a 100 nm thick doped polysilicon layer to approximately 1 ohm/sq. Incomparison with this, the sheet resistance of a doped silicon layerhaving a corresponding thickness is approximately 10 ohm/sq, and a metallayer lies in the mohm/sq range.

Furthermore, the object is achieved, a method of the type mentioned inthe introduction, by virtue of the fact that:

-   -   the first insulation layer is removed, at least partly, as far        as the buried layer, and    -   directly before the production of an emitter contact, of a base        contact and of a collector contact, a silicide region is made        available on the buried layer,    -   the silicide region being formed in such a way that the        collector contact is connected to the collector zone in a        low-impedance manner.

This makes it possible, without additional process complexity, toproduce a high-frequency bipolar transistor which combines both a smallspace requirement and a low collector resistance and hence a hightransition frequency.

In contrast to known methods, such as the so-called buried metal method,in which the buried layer is silicided directly after it has beenproduced, or is even completely composed of metal, in this case theburied layer is not silicided until after the bipolar transistor hasbeen completely finished, directly prior to the beginning of theproduction of the contacts (of the electrodes). This avoids theapplication of metal while the transistor is actually being produced,and hence also metal contaminations which make such a processimplementation incompatible and unsuitable for present-day transistorproduction methods.

The silicide region is typically formed with a thickness of between 10and 200 nm, preferably 100 nm.

Another configuration of the method according to the invention providesfor a transition metal, preferably titanium or cobalt, to be used forforming the silicide region. Said transition metal forms thecorresponding transition metal silicide with silicon. A transition metalthat yields a minimum sheet resistance of the buried layer is typicallychosen.

In a further development of the method according to the invention, boththe first insulation layer and the second insulation layer are removed,at least partly, so that the buried layer and the base connection regionare at least partly uncovered and can be silicided. The insulationlayers usually comprise silicon oxide or silicon nitride. The insulationlayer can thus be removed using phosphoric acid in the case of siliconnitride, and using hydrofluoric acid in the case of silicon oxide. Ifboth insulation layers are composed of the same material, there is noneed for an additional process step for the etching. If the insulationlayers are composed of different materials, after the etching of thefirst insulation layer the etchant is changed for the etching of thesecond insulation layer.

After the etching, both the base connection region and the buried layerare uncovered, at least partly, and can be silicided. In order to avoidan undesirable incipient etching of other chip regions, e.g. ofinsulation zones or other components, during the etchings, the etchingmay be effected with the aid of a mask. The mask is removed in theregions in which etching is intended to be effected, and the otherregions remain covered.

The etching is usually effected wet-chemically on account of the highselectivity. In principle, however, it is also possible to usedry-chemical etching methods.

A preferred development of the method according to the inventionprovides for the silicide region to be formed in a self-aligned mannerwith respect to the base connection region. In this case, a silicideregion is formed only on silicon; regions such as e.g. silicon oxide orsilicon nitride are not silicided. Such a so-called “salicide method”(salicide=self-aligned silicide) is known from DE 19958062 by way ofexample.

The definition of the position of the silicide region on the buriedlayer thus takes place without the aid of photolithography. This meansthat the silicide region can be kept relatively small, for example inthe range of between 0.25 and 0.35 μm.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a schematic cross-sectional view of a known bipolartransistor;

FIG. 2 shows a schematic plan view of a known bipolar transistor inwhich the buried layer is provided with a collector contact on one side;

FIG. 3 shows a schematic plan view of a known bipolar transistor inwhich the buried layer is provided with a collector contact on twosides;

FIG. 4 shows a schematic plan view of a known bipolar transistor inwhich the buried layer is provided with a collector contact annularlyaround the transistor;

FIG. 5 shows a schematic plan view of a bipolar transistor according tothe invention with a buried layer silicided in annular fashion,self-aligned with respect to the base connection region;

FIG. 6 shows a schematic plan view of a bipolar transistor according tothe invention with a partly silicided buried layer, self-aligned withrespect to the base connection region;

FIG. 7 shows a schematic cross-sectional view of a bipolar transistorafter the patterning of the emitter connection region; and

FIG. 8 shows a schematic cross-sectional view of a bipolar transistoraccording to the invention after the etching of the insulation layersand after the formation of a silicide region.

DETAILED DESCRIPTION OF THE DRAWINGS AND THE PRESENTLY PREFERREDEMBODIMENTS

FIG. 1 shows a schematic cross-sectional view of a known bipolartransistor 1, in which a buried layer 7 bounded by two insulation zones11, here configured as deep trenches 11, is arranged in thesemiconductor substrate 12. The buried layer 7 is connected via acollector contact 6, which is led out electrically to the surface of thebipolar transistor 1. This enables the bipolar transistor 1 to beintegrated into an integrated circuit.

The bipolar transistor 1 furthermore contains an emitter contact 2adjoining an emitter connection region 3, and also a base contact 4. Inorder to reduce the base resistance, as illustrated in FIG. 1, asilicided base connection region 13 is provided on a base connectionregion 5, said base connection region 13 connecting the base contact 4to the base connection region 5. Such a bipolar transistor 1 isdescribed in DE 199 58 062 by way of example.

The base zone 15 beneath the emitter connection region 3 may comprisesilicon-germanium SiGe has and a thickness of between 1 nm and 200 nm,typically 30 nm. The collector zone 14 is arranged beneath the base zone15 in a manner adjoining the buried layer 7. Said buried layer 7 isprovided with a collector contact 6 only on one side of the bipolartransistor 1 in FIG. 1.

FIG. 2 schematically shows a plan view of a bipolar transistor in whichthe buried layer 7 is provided with a collector contact 6 on a singleside. The base connection region 5 is connected by a base contact 4, andthe emitter connection region 3 is connected by an emitter contact 2. Insuch a configuration, although the bipolar transistor 1 has a small areadetermined by the extent of the buried layer 7, the collector region(not illustrated here), on account of the relatively large sheetresistance of the buried layer 7, is connected by the collector contact6 only on one side.

Smaller collector resistances can be obtained by the buried layer 7being connected not just on one side, as in FIG. 2, but also on theopposite side, as shown schematically in a plan view in FIG. 3. Thebipolar transistor 1 from FIG. 3 has a resistance with a magnitudeapproximately half that of the bipolar transistor 1 from FIG. 2.

However, it becomes clear that the area occupied by the buried layer 7is larger than the buried layer 7 of the bipolar transistor from FIG. 2.The additionally required area of the buried layer 7 results from thewidth X1 of the collector contact 6, the distance X2 between thecollector contact 6 and the base connection region 5, and an overhang X4of the buried layer 7, the overhang X4 in FIG. 3 representing thedistance between the collector contact 6 and the closest edge of theburied layer 7.

This additionally required area is given by the availablephotolithography and alignment tolerances. Typical contact hole widthsin photolithography are nowadays 0.5 μm, for example, with alignmenttolerances of 0.25 μm, so that overall the buried layer 7 is widened byapproximately 1 μm if an additional collector contact 6 is provided.

Even lower sheet resistances of the buried layer 7 are obtained if, asshown schematically in FIG. 4, the collector contact 6 and the buriedlayer 7 are provided annularly around the base connection region 5. Inthis case, the collector current can flow on four sides, as a result ofwhich the collector connection resistance is quartered. However, theseenlarged collector contacts 6 lead to significantly enlarged dimensionsof the bipolar transistor 1. In addition to increased production costson account of the larger area required in the semiconductor substrate,the collector-substrate capacitance of the bipolar transistor 1 is alsoincreased proportionally to the increasing area of the buried layer 7.This leads to a longer gate delay time of the transistor or an increasedpower consumption of integrated circuits.

Therefore, what transistor configuration has been used heretofore hasdepended on whether the transistor is designed for maximum transitionfrequency, as described with reference to FIG. 4, least spacerequirement, as described with reference to FIG. 2, or a compromisebetween the two, as described with reference to FIG. 3.

The bipolar transistor 1 according to the invention from FIG. 5 combinesboth a low collector resistance and hence a high transition frequencyand a small space requirement. The plan view shows that the silicideregion 8 extends around the base connection region 5. In FIG. 5, thewidth X3 of the overlap region between the collector contact 6 and thesilicide region 8 is less than the width X1 of the collector contact 6.

The width X3 of the overlap region and the width X1 of the collectorcontact 6 are typically equal in magnitude. The collector contact 6 canthus cover the silicide region 8 with its entire cross section. Thecollector contact is also connected to the silicide region 8 whenalignment inaccuracies occur.

Furthermore, the buried layer 7, on that side of the collector contact 6which is remote from the base connection region 5, may remainunsilicided, as is shown in FIGS. 5 and 6. This may be advantageous ifother components that are not intended to be silicided are situated verynear. An auxiliary mask that prevents the siliciding can then be chosento be smaller than in the case where the buried layer 7 is completelysilicided, that is to say if the silicide region 8 extends on the entirearea of the buried layer 7. This reduces the possible minimum distancebetween the components and hence the required area of integratedcircuits.

The silicide region 8 has a sheet resistance in the ohm range. The sheetresistance of the buried layer 7 is thus decreased in such a way that,even in the case of a metal contact-connection of the buried layer 7with the aid of the collector contact 6 on only a single side of thebipolar transistor 1, the collector zone is effectively connected inlow-impedance fashion from all sides by means of the silicide region 8.

It is not necessary in this case for the silicide region 8 to be led asa closed ring with respect to the collector contact 6. A significantreduction of the collector resistance already results if the buriedlayer 7 is silicided for example only as far as the end sides of thebipolar transistor 1, as is shown in a schematic plan view withreference to FIG. 6. Here, the silicide region 8 extends at least to thelevel of the emitter contact 2.

This configuration may be favorable for example if, as shown withreference to FIG. 1, the base connection region 5 is partly led via aninsulation zone such as a trench. The transistor dimensions can thus bekept as small as possible.

For the bipolar transistor 1 according to the invention, it isunimportant whether the silicide region 8 covers the entire buried layer7 that is not covered by the base connection region 5, or regions of theburied layer 7 remain unsilicided, as long as there is a continuousconnection from the silicide region 8 to the collector contact 6.

A description is given below, with reference to FIGS. 7 and 8, of how asilicide region 8 is produced in a self-aligned manner with respect tothe base connection region 5, without significant additional outlay incomparison with known production methods.

Firstly, a bipolar transistor 1 is produced in a known manner, with theproduction of a buried layer 7, a collector zone 14, a first insulationlayer 10 on the buried layer 7 and the collector zone 14, a base zone 15on the collector zone 14, a base connection region 5, a secondinsulation layer 9 on the base connection region 5, and an emitterconnection region 3. The emitter region, which adjoins the base region15, is not shown.

Both the second insulation layer 9 and the first insulation layer 10 maybe composed of silicon oxide or silicon nitride, for example. The firstinsulation layer 10 may have a thickness of a few 100 nm, preferably 100to 600 nm, and the second insulation layer 9 may have a thickness ofbetween 50 and 300 nm. Generally, the first insulation layer 10 isthicker than the second insulation layer 9.

The buried layer 7 typically comprises a 1 to 9 μm highly doped siliconlayer, the collector zone 14 typically comprises a 100 to 1000 nm thickepitaxial silicon layer, and the base connection region 5 typicallycomprises a 50 to 300 nm thick highly doped polysilicon layer.

Such a known method for the production of a bipolar transistor 1 isdescribed in detail in DE 199 58 062 C2, by way of example.

In the method according to the invention, it is then preferably thecase, as shown with reference to FIG. 8, that the first insulation layer10 is removed above the buried layer 7, using hydrofluoric acid in thecase of silicon oxide and using phosphoric acid in the case of siliconnitride. This etching takes place in a self-aligned manner with respectto the base connection region 5. In order to avoid an undesirableincipient etching of other chip regions during these etchings, theetchings may be effected with the aid of a mask, which may be made ofresist, for example, which covers regions in which etching is notintended to be effected, and only the regions which are intended to besilicided in a subsequent method step are left free.

It is conceivable for only the first insulation layer 10 to be removedcompletely as far as the buried layer 7 in order to produce a silicideregion 8 in the buried layer 7.

For the production of the silicide region 8, it is possible, by way ofexample, either to apply a metal directly (e.g. with the aid ofsputtering) and to convert the surface of the buried layer 7 and of themetal into a silicide, or to apply a silicide directly. The thickness ofsuch a silicide region 8 is typically in the range of between 10 and 200nm.

If, besides the buried layer 7, the base connection region 5 is alsoadditionally intended to be silicided, the second insulation layer 9 islikewise removed. If the second insulation layer 9 and the firstinsulation layer 10 are composed of the same material, then it isusually not even necessary to lengthen the etching time for thispurpose, since the first insulation layer 10 is generally thicker thanthe second insulation layer 9. If the insulation layers 9 and 10 arecomposed of different materials, after the etching of the secondinsulation layer 9 the etchant is changed for the removal of the firstinsulation layer 10.

Both the second insulation layer 9 and the first insulation layer 10 mayin each case be constructed from different layers. The etchings are thento be performed in such a way that at least all the layers of saidinsulation layers 9 and 10 are removed.

The method described above has the effect that the buried layer 7 issilicided in a self-aligned manner with respect to the base connectionregion 5. The silicide region 8 on the buried layer 7 is therebyarranged on a gradient aligned with respect to the outer boundary of thebase connection region 5, that is to say that the silicide region 8directly adjoins the base connection region 5 in a plan view, as can beseen from FIGS. 5 and 6. Particularly small dimensions of the bipolartransistor 1 are thereby possible, smaller than those produced by meansof photolithography. Further advantages of self-alignment consist in thesymmetrical construction of the bipolar transistor 1. Moreover, lowercosts are incurred than in the case of aligned methods, since nolithography is required.

Afterward, the bipolar transistor 1 is completed in the customarymanner, that is to say that a dielectric is deposited which covers theentire bipolar transistor 1. Afterward, metal contacts, the emittercontact, the base contact and the collector contact, are produced andmetallization planes are deposited.

The method described above can be employed both for self-aligned doublepolysilicon transistors, that is to say those transistors in which theemitter and base connection regions are in each case composed ofpolysilicon and are self-aligned with respect to one another, and forpolytransistors or aligned transistors.

What is achieved overall by means of the invention is that ahigh-frequency bipolar transistor is provided which combines both asmall space requirement and thus a lower power consumption, and a lowcollector resistance and hence a high transition frequency with oneanother. Moreover, a method according to the invention has beenpresented which makes it possible to produce a high-frequency bipolartransistor having the properties mentioned above, without additionalprocess complexity.

In comparison with known bipolar transistors with the same spacerequirement, the high-frequency bipolar transistor according to theinvention has a lower collector resistance and hence a better transistorperformance, such as a higher transition frequency, shorter gate delaytimes, or a lower power consumption of integrated circuits. Theproduction costs are comparable in this case.

In comparison with known high-frequency bipolar transistors with anannularly connected collector, the high-frequency bipolar transistoraccording to the invention exhibits similarly fast transitionfrequencies, but with significantly lower production costs on account ofthe smaller space requirement, and a lower power consumption on accountof the smaller collector-substrate capacitance.

It is therefore intended that the foregoing detailed description beregarded as illustrative rather than limiting, and that it be understoodthat it is the following claims, including all equivalents, that areintended to define the spirit and scope of this invention. Nor isanything in the foregoing description intended to disavow scope of theinvention as claimed or any equivalents thereof.

1. A high-frequency bipolar transistor comprising: an emitter contactelectrically connected to an emitter connection region; a base contactelectrically connected to a base connection region; a collector contactelectrically connected to a collector connection region, the collectorconnection region including a buried layer, the buried layerelectrically connecting the collector contact to a collector zone; asilicide region provided on the buried layer, the silicide regionelectrically connecting the collector contact to the collector zone;wherein the silicide region extends around the base connection region;and wherein the collector contact does not extend around the baseconnection region.
 2. The bipolar transistor as claimed in claim 1,wherein a width of overlap between the collector contact and thesilicide region is less than a width of the collector contact.
 3. Thebipolar transistor as claimed in claim 1, wherein the silicide regioncovers the entire buried layer other than that on which the baseconnection region is disposed.
 4. The bipolar transistor as claimed inclaim 1, wherein the silicide region is a salicide region.
 5. Ahigh-frequency bipolar transistor comprising: an emitter contactelectrically connected to an emitter connection region; a base contactelectrically connected to a base connection region; a collector contactelectrically connected to a collector connection region, the collectorconnection region including a buried layer, the buried layerelectrically connecting the collector contact to a collector zone; asilicide region provided on the buried layer, the silicide regionelectrically connecting the collector contact to the collector zone;wherein the silicide region extends around the base connection region;and wherein the silicide region does not extend to a side of thecollector contact which is farther from the base connection region thanan opposing side of the collector contact.
 6. The bipolar transistor asclaimed in claim 5, wherein a width of overlap between the collectorcontact and the silicide region is less than a width of the collectorcontact.
 7. The bipolar transistor as claimed in claim 5, wherein thesilicide region covers the entire buried layer other than that on whichthe base connection region is disposed.
 8. The bipolar transistor asclaimed in claim 5, wherein the silicide region is a salicide region.